1. Field of the Invention
The invention relates generally to access devices, semiconductor devices incorporating an access device, and methods of fabricating same. More particularly, the invention relates to an access device having a vertically oriented channel and related semiconductor devices and methods of fabrication.
2. Description of Related Art
The operation of modern electronics is largely predicated upon the performance capabilities of the individual elements arranged to form semiconductor devices. The dynamic random access memory (DRAM) is an excellent contemporary and historical example of a semiconductor device. The DRAM is widely used in computer systems and other consumer electronics to store data. Their data storage capabilities have increased dramatically over the years as the elements implementing the DRAM have been substantially reduced in size without loss of functionality.
A DRAM may be understood as a vast array of memory cells arranged at the respective intersections of a matrix of row-wise word lines and columnar bit lines. Each memory cell typically includes an access element such a field effect transistor (FET) coupled to a storage element such as a capacitor. The access element allows the transfer of electrical charge from/to the storage element during read/write operations according to control voltages applied to a gate region of the access element.
The storage capacity per unit size of a DRAM is dictated to a large extent by the maximum possible integration density for the memory cells forming the memory cell array. In turn, the size of (i.e., the area occupied by) the constituent access elements and storage elements determines the maximum possible integration density. Accordingly, research and development efforts have been constantly expended in attempts to minimize the size of access elements and storage elements and improve integration density.
As a practical matter the integration density of a semiconductor device is limited by the collection technologies used to fabricate it. That is, the constellation of available technologies applied to the fabrication of a semiconductor device defines the physical scale of the individual elements forming the semiconductor device. This scale or feature size “F” may be used to designate minimum relative geometries for the elements, and largely determines the maximum integration density for the resulting semiconductor device. For example, Figure (FIG.) 1 is a graph illustrating a relationship between shrinking design rules, as indicated by the descending plot of squares, and various DRAM design families, as indicated by the plots of triangles (an 8F2 family), inverted triangles (a 6F2 family), and circles (a 4F2 family).
Existing and extrapolated die counts per fabrication wafer are shown for each design family over a period of time ranging from year 2002 through year 2010. Clearly, a move towards the 4F2 family of semiconductor devices will result in a greater number of die yielded per fabrication wafer. Such yield increase has important consequences to the profitability of semiconductor manufacturing operations.
However, in order to fabricate reliable semiconductor devices at a 4F2 scale, considerable additional attention must be directed to minimizing the size of constituent elements without loss of functionality. In this vein, the area occupied in a memory cell matrix by individual memory cells has been reduced by replacing laterally oriented access elements (i.e., access elements having a principal channel formed in the X/Y plane) with vertically oriented access elements (i.e., access elements having a principal channel formed in the Z plane orthogonal to the X/Y plane). Of course, the designation of X, Y, and Z orientations is an arbitrary one typically made in relation to the principal working surface of a substrate, but for clarity of description relative to the related drawings such designations are quite helpful. So, in the description that follows a convention will be adopted that assumes the X and Y directions are consistent with the orientation of word and bits lines running across a principal surface of a substrate, and that the Z direction is orthogonally “vertical” relative to this “lateral” X/Y plane.
With this convention is place, FIGS. 2A, 2B and 2C are considered. FIG. 2C is a perspective illustration showing a portion of a conventional DRAM memory cell matrix incorporating individual memory cells including a vertically oriented access element. Each access element has a vertically oriented channel extending in the Z direction from a buried bit line (BBL) region 2 formed on an isolation region 1 of a substrate to a storage node 5 formed above a word line 4. The vertical channel is implemented as a silicon pillar extending upward from the substrate. The transfer of electrical charge through the vertical channel is controlled by a gate 3. The term “pillar” in this context assumes a similar convention to that described above which assumes a horizontally disposed substrate populated by columnar or pillar shaped structures extending vertically (in the Z direction) from the substrate. The term pillar subsumes vertical structures having any reasonable aspect ratio.
As may be seen from reference to FIGS. 2A and 2B, individual memory cells including this type of vertically oriented channel may be more densely grouped together in a memory cell array in comparison with conventional memory cells incorporating access elements including a laterally oriented channel. That is, FIG. 2A is a top down illustration of a memory cell array defined by pillar mask patterns having a 2F by 2F cell matrix layout. FIG. 2B further illustrates this memory cell array by showing constituent word lines, bit lines, and an insulating oxide spacer.
Unfortunately, conventionally formed access devices including vertically oriented channels suffer from a number of performance and fabrication issues. A first class of these issues relates to the formation of a connection line (e.g., a word line in the context of a semiconductor memory device connecting a row of memory cells). Conventionally, connection lines such as word lines and gate electrodes associated with a connected access element are separately fabricated. This approach not only requires the application of two separate fabrication processes, but also suffers from problems associated with elevated connection line resistance caused by the presence of natural oxides or other contamination layers between the connection line and the gate electrode.
Another class of issues relates to the contact resistance between a subsequently formed connection (e.g., a storage element in the context of a semiconductor memory device) and an access element having a vertically oriented channel. Here again, contamination and/or abuse from fabrication processes may result in the formation of natural oxides, other contamination layers or material layer damage that results in elevated contact resistance between a subsequently element and an upper end of the vertically oriented access element (e.g., an upper source/drain region).
At least in the context of a RAM devices, vertically oriented access elements frequently result in high levels of gate induced drain leakage (GIDL). GIDL has adverse consequences to the refresh rate and power consumption of a memory device incorporating the access element.
Another class of fabrication related issues plaguing vertically oriented access elements in the context of semiconductor memory devices concerns the nature and geometric orientation or alignment of a buried bitline (BBL) structure. For reasons well understood in the art, a lightly doped (LD) structures are often preferred for the formation of lower source/drain regions associated with BBL structures. However, the formation of a LD lower source/drain region has proven to be a difficult task, requiring numerous fabrication steps and often resulting in alignment problems.
Taken as a collection, these continuing issues and others related to the design and fabrication of semiconductor devices incorporating access elements having a vertically oriented channel have greatly impeded manufacturers' practical ability to fabricate such devices at acceptable cost points and reliability expectations.